Mohamed ABDMOULEHMy task is to design the CMOS Analog Integrated Circuits by following the Analog Flow Design.
(Project Specifications, Requirements, Schematic, Sizing Transistors (CMOS Process), Simulation (Operating Point, Gain, Phase, Noise...), Layout (DRC, Extract, LVS), Post-Layout Simulation, GDSII, Layout Virtuoso, Diva, matching, Common Centroide, Analog Layout, Simulation Eldo & Spectre, Design of CMOS Operational Amplifier, Verification, DRC, LVS, Cadence, Checklists, Technology 0.5um & 90nm & 65nm.. My new task is to design the Printed Circuits Board (PCB): Circuit design and analysis, PCB layout, BOM creation, engineering documentation, PCB design, and Electronic system cost reduction and optimization. • Electronic And Microelectronic Background • Analog Design • CMOS Operational Amplifier • Voltage Controlled Oscillator • Analog Layout Technics • Cadence Tool & Environment • Altium Designer Summer08 • PADS Logic
Electronique Microelectronique Layout Analogique Cadence Altium Designer Pads Logic Analog Integrated Circuits Design Pcb Design Ingénieur Electrique
Formations de Mohamed ABDMOULEHGénie electriqueEcole Nationale des Ingénieurs de Sfax (ENIS)Ingénieur Spécialité électronique et microélectronique • Specific Courses : Design of Integrated Circuits FPGA, Custom and MEMS, Electronic Noise, The Advanced Processor Architecture, Networks, Architecture and VLSI Circuits Logic Circuits, Digital Signal Processing, Video Communication Systems and Coding, Programming (C, VHDL, object-oriented , Assembler), Design of Analog and Digital MOS Circuits, CAD Electronics and Microelectronics, ... • Other Courses : Conduct of Business Projects, Technical English, Production Management, Probability and Statistics, Process Engineering, General Economics... Final Graduation Project: Design of 65nm CMOS Ring Oscillator with Low Phase Noise - STMicroelectronics Rabat - Morocco. M. Mohamed ABDMOULEH, M. Mounir SAMET, M. Ahmed FAKHFAKH, M. Mourad LOULOU from National Engineering School of Sfax in TUNISIA -- M. Mohamed Halim SBAA & M. Soufiane AIT ALI OUMANSOUR from STMicroelectronics in Morocco Expériences professionnelles de Mohamed ABDMOULEHTraining analog ic design engineerSTMicroelectronics
Study of a Ring Oscillator based with CMOS Invertors - at STMicroelectronics Rabat – Morocco– This training was an opportunity to practice the skills learned during my studies, especially regarding: Design of Analog MOS circuits, oscillators and PLL, electronic Analog... • Initiation with design tool CADENCE. • Determination of the parameters of the 65nm CMOS technology. • Characterisation (jitter, phase noise, consummation) Knowledge on following STMicroelectronics’ process and flow: CMOS65 Design with transistors LVT HVT SVT, High speed, Low Leakage Design environment is Cadence Simulators: Eldo Training analog ic design engineerSTMicroelectronics
Final Graduation Project : Design of 65nm CMOS Ring Oscillator with Low Phase Noise – at STMicroelectronics Rabat – Morocco – Design of a Ring Voltage Controlled Oscillator (VCO) based with a delay cell for the 65nm CMOS technology, which aims to improve the phase noise while ensuring oscillation frequency of 432Mhz. the aim of this project was essentially to propose a simple design clear which is based on theoretical concepts of Analog blocks that make up our system. M. Mohamed ABDMOULEH, M. Mounir SAMET, M. Ahmed FAKHFAKH, M. Mourad LOULOU from National Engineering School of Sfax -- M. Mohamed Halim SBAA & M. Soufiane AIT ALI OUMANSOUR from STMicroelectronics • Study and modelling the phase noise. • Sizing of the cell. • Characterisation by simulating the entire VCO with output buffer. • Characterisation (jitter, phase noise, consummation) Analog ic design & layout engineerTelnet
My task is to design the CMOS Analog Integrated Circuits by following the Analog Flow Design. (Project Specifications, Requirements, Schematic, Sizing Transistors (CMOS Process), Simulation (Operating Point, Gain, Phase, Noise...), Layout (DRC, Extract, LVS), Post-Layout Simulation, GDSII, Layout Virtuoso, Diva, matching, Common Centroide, Analog Layout, Simulation Eldo & Spectre, Design of CMOS Operational Amplifier, Verification, DRC, LVS, Cadence, Checklists, Technology 0.5um & 90nm & 65nm.. Design of a CMOS Operational Amplifier : Front-end and Back-end 24 Bit Sigma Delta DAC for Audio Applications Project Design and the implementation of the Analog part of 24 bits Switched Current Sigma Delta DAC used for audio applications. Participate in the Digital Analog Converter project (CMOS process) • Design of the Operational Amplifier. • Review of the Back-end part of the DAC. • Simulators: Spectre, Spectre RF • Layout: layout XL, DRC, LVS with DIVA CMOS Operational Amplifier, Cadence, layout XL, DRC, LVS with DIVA Design and implementation of a Recovery Circuit Energy of a passive RFID Chip Passive RFID ISO/IEC 15693 Project Design and implementation of a Recovery Circuit Energy of a passive RFID Chip Review of the: • Design and characterization of : RF_Limiter, OTA, Bandgap • Realization of the Ring layout for the test-chip RF • Layout: layout XL, DRC, LVS with DIVA RF_Limiter, OTA, Bandgap, Cadence, layout XL, DRC, LVS with DIVA Layout of CMOS Filter GmC ALLOUIS Receiver - Mixer & Low Pass Filter - Project This project focuses on the implementation of the analogue part of the receiver and especially the mixer and the low pass filter. These blocks are implemented in 0.5µm CMOS technology. Back-end of CMOS Filter GmC • Design of Mixer Block • Responsible of the Back-end part of the Filter • Layout: layout XL, DRC, LVS with DIVA Advanced training techniques of Analog Layout, cadence, layout XL, DRC, LVS with DIVA Design and Layout of CMOS Ring Voltage controlled Oscillator Start-up Project • Design of Ring VCO with SCMOS3 0.5µm technology • Training on the design of CMOS Analog circuits. • Advanced training techniques of Analog Layout. • Layout of the VCO: Control Stage, Delay Cell, Buffer • Layout: layout XL, DRC, LVS with DIVA Advanced training techniques of Analog Layout, VCO, layout XL, DRC, LVS with DIVA Pcb design & layout engineerTelnet
Responsibilities included: Circuit design and analysis, PCB layout, BOM creation, engineering documentation, PCB design, and Electronic system cost reduction and optimization. Re-engineering of two products of “Chauvinx-Arnoux” Following the obsolescence of the S1D15400 display controller of “EPSON”, “Chauvin-Arnous” wishes to conduct re-engineering of 2 products. The solution is to replace the S1D15400 by the R8C/L38A microcontroller of Renesas while keeping full functionality and without affecting other parts of the two cards. • Schematic, BOM, Specification document, Design document Electronic Design, PADS Logic, Schematic Design and Layout of Terminal Display for a Navigation System (GPS) for automotive applications PCB redesign according to the new specifications of an IO Protection Circuit: updated components (placement & routing), area optimisation, and cost optimisation. • Schematic, Layout, DRC, BOM, Specification document, Design document Electronic Design, Altium Designer Summer08, Schematic & PCB Layout |
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